@ARTICLE{8669820,
author={D. {Pedretti} and M. {Bellato} and R. {Isocrate} and A. {Bergnoli} and R. {Brugnera} and D. {Corti} and F. {Dal Corso} and G. {Galet} and A. {Garfagnini} and A. {Giaz} and I. {Lippi} and F. {Marini} and G. {Andronico} and V. {Antonelli} and M. {Baldoncini} and E. {Bernieri} and A. {Brigatti} and A. {Budano} and M. {Buscemi} and S. {Bussino} and R. {Caruso} and D. {Chiesa} and C. {Clementi} and X. F. {Ding} and S. {Dusini} and A. {Fabbri} and R. {Ford} and A. {Formozov} and M. {Giammarchi} and M. {Grassi} and A. {Insolia} and P. {Lombardi} and F. {Mantovani} and S. M. {Mari} and C. {Martellini} and A. {Martini} and E. {Meroni} and L. {Miramonti} and S. {Monforte} and P. {Montini} and M. {Montuschi} and M. {Nastasi} and F. {Ortica} and A. {Paoloni} and E. {Previtali} and G. {Ranucci} and A. C. {Re} and B. {Ricci} and A. {Romani} and G. {Salamanna} and F. H. {Sawy} and G. {Settanta} and M. {Sisti} and C. {Sirignano} and L. {Stanco} and V. {Strati} and G. {Verde}},
journal={IEEE Transactions on Nuclear Science},
title={Nanoseconds Timing System Based on IEEE 1588 FPGA Implementation},
year={2019},
volume={66},
number={7},
pages={1151-1158},
keywords={buffer circuits;clocks;field programmable gate arrays;finite state machines;protocols;synchronisation;trigger circuits;computers Ethernet-based local area network;timing receiver nodes;message-based synchronization system;backend electronics;serial data streams synchronization;global clock domain;hardware-based finite state machine;timing system;point-to-point data links;IEEE 1588 FPGA implementation;clock synchronization procedures;interaction vertex;distributed data readout topologies;data buffering;network complexity;front-end data buffer capability;trigger validation;field-programmable gate array implementation;IEEE 1588 Precision Time Protocol;European Organization for Nuclear Research;timing trigger and control system;CERN;PTP;LAN;TTC system;star topology configurations;CAT-5e cables;Synchronization;Clocks;Delays;Physics;Protocols;Ethernet;Eye diagram;field-programmable gate arrays (FPGAs);front-end electronics;hardware;synchronization;timing system},
doi={10.1109/TNS.2019.2906045},
ISSN={},
month={July},}